Thin film transistor liquid crystal display (TFT-LCD), which has advantages such as small size, low power consumption, free of radiation and relatively low manufacturing cost, takes a dominant role in the current panel display market.
As shown in FIG. 1 and FIG. 2, in a co-planar thin film transistor (TFT), a source electrode 3, a drain electrode 4 and a gate electrode 1 are arranged at a same side of an active layer 2. According to a position of the gate electrode 1 with respect to the active layer 2, co-planar TFTs can be classified into top-gate co-planar TFT (as shown in FIG. 1) and bottom-gate co-planar TFT (as shown in FIG. 2).
When applying the co-planar TFT into the TFT-LCD, as shown in FIG. 1, for the top-gate co-planar TFT, a pixel electrode 5 is in electrical contact with the drain electrode 4 via a via hole penetrating a passivation layer 102 and a gate insulation layer 101. The via hole has a large depth, so it is difficult for the pixel electrode 5 to climb and the pixel electrode 5 may be prone to be broken, resulting in poor electrical contact. If the electrical connection between the pixel electrode 5 and the drain electrode 4 is realized through jumping connection, a quantity of masks is increased and the production cost is increased. For the bottom-gate co-planar TFT, as shown in FIG. 2, the active layer 2 is provided on the source electrode 3 and the drain electrode 4 through a lap joint. Since lateral surfaces of a source metal and a drain metal are rough due to etching process when forming the source electrode 3 and the drain electrode 4, and the active layer 2 is thin, the climbing problems and breakages may occur in the active layer 2. In addition, in the above case, the active layer 2 has an uneven thickness and the short circuit is prone to be generated.